Common electrode voltages of pixel units on an array substrate should be equal to each other. However in practice, the common electrode voltage Vcom=V−ΔVp, wherein ΔVp is a jumping voltage of pixel voltage Vp caused by switching on/off the pixel through the gate, V is the actual input common voltage. As shown in FIG. 1, it is an equivalent circuit diagram of one of pixels on the array substrate, ΔVp is mainly influenced by the gate-source capacitance Cgs:
                              Δ          ⁢                                          ⁢          Vp                =                                            C              gs                                      C              all                                ⁢                      (                                          V                gh                            -                              V                gl                                      )                                              (        1        )            
Wherein Call is a sum of capacitances in the circuit of FIG. 1 (namely equivalent capacitance), and Vgh and Vgl are high and low electrical level voltages of the gate respectively.
FIG. 2 is a top view of a known array substrate with oxide as an active layer. As shown in FIG. 2, the array substrate comprises a gate line 110, a data line 120, and a TFT (comprising a gate 160, an active layer 130, a source 140 and a drain 170). Typically, the active layer 130 is located over the gate 160 with a gate insulating layer (not shown) interposed therebetween. The drain 170 and source 140 are located over the active layer 130, and there is an etch stop layer (not shown) between the drain 170/source 140 and the active layer 130. The drain 170 and source 140 are connected with the active layer 130 through vias 150 on the etch stop layer, respectively. The projection of active layer 130 is located at the middle of the projection of gate 160. Upper and lower edges of the active layer 130 are apart from respective upper and lower edges of the gate 160 by a small distance. In the manufacturing process, it is possible that process deviation would result in the misalignment of the active layer 130, that is, the projection of active layer 130 is not at the middle of the projection of gate 160 or even beyond edges of the gate 160. As known from the capacitance formula C=∈S/d (where S is the opposite area of parallel plates, ∈ is the dielectric coefficient of dielectric, d is the distance between the parallel plates), misalignment of active layer 130 might cause the average dielectric coefficient ∈ between the gate 160 and source 140 (there are at least a gate insulating layer and an active layer comprised between the gate 160 and source 140) to change, which might result in a large error between Cgs of each pixel unit and the predesigned Cgs. Accordingly, ΔVp would have large error, and a large error between the actual common voltage Vcom applied on the common electrode and the predesigned common voltage would be caused, which may affect the displayed images.